1. Field of the Invention
The present invention relates to a large-scale-integrated circuit (LSI) test data generating system and method. More particularly, the present invention relates to a test data generating system to perform testing of high-speed operation (actual operation) of an LSI with automatic test equipment (ATE) using high-speed operation verifying test data.
2. Description of the Related Art
Various LSI testing techniques are known. For example, a xe2x80x9cfunction testxe2x80x9d technique is known in which the operation of the LSI is tested by directly using a function test pattern (i.e., a test pattern for simulation) for automatic test equipment (ATE).
An advantage of the function test technique is that generation of a new test circuit and a new test pattern are not required because the test pattern which is used for simulation is used directly. A disadvantage of the function test technique is that is impossible to realize a high-speed test (actual operation) because delay of input signals and output signals becomes large as a result of the capacitance of a probe pin and a board on the tester. In particular, the input signal and output signal are dulled to a large extent.
Another conventional LSI testing technique is the BIST technique. The BIST technique tests operation of an LSI device using a data generator and a data compressor built into a chip. A circuit to be tested is arranged between the data generator and the data compressor. Data is input to the circuit to be tested from the data generator and the data compressor receives an output from the circuit to be tested.
High speed operation (actual operation) can be tested using the BIST technique by setting an input clock signal to the clock signal of the high-speed operation (actual operation). Moreover, the data compressor allows the test to be made efficiently.
However, when using the BIST technique, the entire circuit is defined as the test object. Therefore, a test must be conducted for the entire circuit, even for the part of the circuit which does not require the test. As a result, the time required to perform the test increases. The part of the circuit which does not require the test is, for example, a part which does not require the high-speed operation (actual operation) test and a part to which a plurality of flip-flop (FF) circuits are connected. For these parts which do not require the test, it is adequate to latch data with the final-stage FF circuit, and therefore an accurate timing margin is not required for the FF circuits of the stages other than the final stage. Moreover, when using the BIST technique, chip area increases because the data generator and data compressor must be built into the chip.
Another LSI testing technique is the xe2x80x9cpath testxe2x80x9d technique. According to the path test technique, the setup timing and hold timing among flip-flop (FF) circuits are verified by using FF circuits for scanning. By operating the FF circuit for scanning to which a predetermined value is set, it can be verified whether or not data is latched accurately in the FF circuit for scanning in the next stage.
The path test technique allows high-speed operation (actual operation) to be tested by operating the FF circuit for scanning with a clock signal corresponding to the high-speed operation (actual operation). However, because a large number of paths are provided among FF circuits, the time required for testing increases, and it is impossible to test the paths among all FF circuits. Moreover, the chip area increases because the chains of FF circuits for scanning the data must be built into the chip.
Yet another LSI circuit testing technique performs testing using a ring oscillating circuit. More specifically, the LSI operation test is conducted by providing a ring oscillating circuit within a chip. Operations of the LSI circuit can be verified by obtaining an output result of the LSI in synchronization with an output frequency of the ring oscillating circuit.
Testing using the ring oscillating circuit allows high-speed operation (actual operation) to be tested by setting the output frequency of the ring oscillating circuit to the frequency of the high-speed operation.
However, the ring oscillating circuit test is an indirect LSI operation test because the LSI operation test is not conducted with the clock signal supplied to the LSI. Specifically, operation of the LSI is only verified from the external side in synchronization with the output frequency of a ring oscillating circuit. Moreover, the chip area also increases because the ring oscillating circuit must be built into the chip.
Thus, in summary, the conventional LSI testing techniques result in the following problems: (1) the function test technique does not allow high-speed operation (actual operation) to be tested with the tester (ATE). Moreover, even when the high-speed operation (actual operation) can be tested without use of a tester (ATE), (2) the test time increases, and (3) the chip area increases.
Therefore, an LSI testing technique is needed which can test high-speed operation (actual operation) without resulting in an increase in test time and chip area.
It is an object of the present invention to provide an LSI circuit testing system and method which overcomes the above-noted problems of the conventional testing techniques.
Objects and advantages of the present invention are achieved in accordance with embodiments of the present invention with a selecting device to select a first output expectation value corresponding to an input value from simulation data; an inserting device to insert a predetermined number of output expectation values, which are identical to the first output expectation value, after the first output expectation value, and to insert a predetermined number of input values, which are identical to the input value, after the input value corresponding to the first output expectation value; a replacing device to replace the predetermined number of output expectation values of the simulation data with third output expectation values; and a setting device to set the first output expectation value to a second output expectation value determined from the simulation data based on the predetermined number or the third output expectation values.
In accordance with embodiments of the present invention, the predetermined number is a number of cycles during which a clock signal is stopped.
In accordance with embodiments of the present invention, the third output expectation value is a don""t care pattern.
In accordance with embodiments of the present invention, the number of cycles to stop the clock signal is determined based on capacitance of elements of a tester.
In accordance with embodiments of the present invention, the number of cycles to stop the clock signal is determined on the basis of the operating conditions of an LSI.
In accordance with embodiments of the present invention, the first output expectation value is selected for every predetermined cycle.
In accordance with embodiments of the present invention, the second output expectation value corresponds to a last cycle in the number of cycles during which the clock signal is stopped.
In accordance with embodiments of the present invention, the test data generating system further comprises a strobe timing generating device to generate a strobe timing to set an output expectation value for the selected output expectation value, wherein the strobe timing is set after the leading edge of the clock signal.
In accordance with embodiments of the present invention, the second output expectation value corresponds to clock cycles after the number of clock cycles during which the clock signal is stopped.
In accordance with embodiments of the present invention, the test data generating system further comprises a strobe timing generating device to generate a strobe timing to set an output expectation value for the selected output expectation value, wherein the strobe timing is set before the leading edge of the clock signal.
Objects and advantages of the present invention are achieved in accordance with embodiments of the present invention with a semiconductor integrated circuit, comprising a high-speed operation verifying control terminal; and a system clock control circuit to stop a clock signal for a predetermined period based on a control signal input to the high-speed operation verifying control terminal, wherein a test is conducted on a tester with test data which is formed to obtain a predetermined output expectation value after the clock signal is stopped for the predetermined period.
Objects and advantages of the present invention are achieved in accordance with embodiments of the present invention with a test data generating system, comprising means for selecting a first output expectation value from simulation data, the first output expectation value corresponding to an input value; means for inserting a predetermined number of output expectation values, which are identical to the first output expectation value, after the first output expectation value; means for inserting a predetermined number of input values, which are identical to the input value, after the input values corresponding to the first output expectation value; means for replacing the predetermined number of output expectation values of the simulation data with third output expectation values; and means for setting a second output expectation value determined from said simulation data to said first output expectation value based on the predetermined number or said third output expectation values.
Objects and advantages of the present invention are achieved in accordance with embodiments of the present invention with a computer readable storage medium encoded with processing instructions for implementing a test data generating method with a computer, the method comprising selecting a first output expectation value from simulation data, the first output expectation value corresponding to an input value; inserting a predetermined number of output expectation values, which are identical to the first output expectation value, after the first output expectation value; inserting a predetermined number of input values, which are identical to the input value, after the input values corresponding to the first output expectation value; replacing the predetermined number of output expectation values of the simulation data with third output expectation values; and setting a second output expectation value determined from said simulation data to said first output expectation value based on the predetermined number or said third output expectation values.
Objects and advantages of the present invention are achieved in accordance with embodiments of the present invention with a test data generating method, comprising selecting a first output expectation value from simulation data, the first output expectation value corresponding to an input value; inserting a predetermined number of output expectation values, which are identical to the first output expectation value, after the first output expectation value; inserting a predetermined number of input values, which are identical to the input value, after the input values corresponding to the first output expectation value; replacing the predetermined number of output expectation values of the simulation data with third output expectation values; and setting a second output expectation value determined from said simulation data to said first output expectation value based on the predetermined number or said third output expectation values.
In accordance with the present invention, the test data generating system provides easy testing of high-speed operation (actual operation) of an LSI using automatic test equipment (ATE) without resulting in an increase of test time and chip area.
In accordance with the present invention, the following advantageous effects are attained. A high-speed operation (actual operation) test can be conducted with the tester (ATE) using high-speed operation verifying test data which takes into considered delay of input signals and output signals as a result of capacitance of a probe pin and a board of the tester. Because only the pattern for simulation is converted to the high-speed operation verifying test data, the data for testing high-speed operation (actual operation) can be obtained easily and the test period can also be reduced. Further, because a chip in accordance with the present invention comprises only a system clock control circuit for controlling the clock signal and a high-speed operation verifying control terminal (clock enable terminal), test can be conducted without increasing the chip area.